1. Field of the Invention
This invention relates to a semiconductor device and a method of manufacturing thereof; in particular to a semiconductor device and a method of manufacturing thereof which can secure margin of a contact process and extremely increased capacitance of a capacitor in restricted area by alternately disposing capacitors, which are formed around a central word line, in front and backside of a semiconductor substrate.
2. Description of the Prior Art
Generally, as a semiconductor device becomes high integration and miniaturization, occupied area of each element of the semiconductor device is reduced. Although size of the semiconductor device is reduced, it is required to secure a minimum capacitance of a capacitor which is necessary to drive the semiconductor device. To secure the capacitance, a charge storage electrode of a capacitor has being manufactured in three-dimensional structure such as a stack structure, a pin structure and a cylinder structure.
FIGS. 1A to 1C are sectional views for explaining a conventional semiconductor device and a method of manufacturing thereof.
Referring to FIG. 1A, an active region is defined by forming an isolation layer 2 on a semiconductor substrate 1. The isolation layer 2 is formed by filling a trench with insulation material such as oxide, in which the trench is formed by etching the semiconductor substrate 1 with desired depth. A first word line 4A and a second word line 4B are formed on the semiconductor substrate 1 of the active region. The first and second word lines 4A and 4B are electrically isolated from the semiconductor substrate by a gate insulation layer 3 and electrically isolated from the outside by a first cap insulation layer 5 and a first spacer insulation layer 6. A first source 7A, a second source 7B and a common drain 7C are formed in the semiconductor substrate by means of an ion implantation process for source and drain regions. The first source 7A is disposed at the outside of the first word line 4A and the second source 7B is disposed at the outside of the second word line 4B and the common drain 7C is disposed between the first and second word lines 4A and 4B. A first inter-insulation layer 8 is formed on an entire structure including the first and second word lines 4A and 4B. Contact holes are formed by etching portions of the inter-insulation layer 8 by a self align contact process so that-the first and second sources 7A and 7B and the common drain 7C are exposed. By polysilicon deposition and chemical mechanical polishing process, the contact holes are only filled with polysilicon, whereby a first contact plug 9A connected to the first source 7A, a second contact plug 9B connected to the second source 7B and a bit line contact plug 9C connected to the common drain 7C are formed.
Referring to FIG. 1B, a bit line 10 is formed on the first inter-insulation layer 8, in which the bit line 10 is electrically connected to the common drain 7C through the bit line contact plug 9C. The bit line 10 is isolated from the out side by a second cap insulation layer 11 and a second inter-insulation layer 13. A second inter-insulation layer 13 is formed on an entire structure including the second cap insulation layer 11 and the second spacer insulation layer 12. Portions of the second inter-insulation layer 13 is etched by means of a contact process for a charge storage electrode so that contact holes to expose the first contact plug 9A and the second contact plug 9B are formed. By polysilicon deposition and chemical mechanical polishing process, the contact holes are only filled with polysilicon, whereby a first charge storage electrode contact plug 14A connected to the first contact plug 9A, a second charge storage contact plug 14B connected to the second contact plug 9B are formed.
Referring to FIG. 1C, a first charge storage electrode 15A connected to the first charge storage electrode contact plug 14A and a second charge storage 15B connected to the second charge storage electrode contact plug 14B are formed by means of the polysilicon deposition and patterning processes. A dielectric film 16 is formed on a surface of the first and second charge storage electrodes 15A and 15B and a plate electrode 17 is formed on the dielectric film 16, thereby forming a capacitor. Thereafter, a third inter-insulation layer 18 is formed so that the capacitor is covered.
In case of manufacturing a semiconductor device by the above conventional method, since the semiconductor device becomes high integration and miniaturization, distance between the first and second charge storage electrode contact plugs 14A and 14B is shorted and area of the first and second charge storage electrodes is also reduced. There is a limit to reduce area of the first and second charge storage electrodes since they are disposed to neighbor from each other. Also, Although size of the semiconductor device is reduced, it is required to secure a minimum capacitance of a capacitor which is necessary to drive the semiconductor device. To secure the capacitance, a charge storage electrode of a capacitor has being manufactured in three-dimensional structure but it is a problem in that a manufacturing process is difficult. If a process margin between a charge storage electrode contact plug and a charge storage electrode is insufficient, the charge storage electrode contact plug is attacked due to misalignment occurred when an etching process for forming the charge storage electrode is performed, whereby a device is not normally operated. In addition, in a device applying a design rule of 0.13 xcexcm, an etching target must be over 10,000 xc3x85 to form a charge storage electrode having a simple stack structure. Accordingly, it is a burden to the etching process and it is a problem in that distance between charge storage electrodes is short and the electrodes are shorted.
Therefore, it is an object of the invention to provide a semiconductor device and a method of manufacturing thereof, which can secure margin of a contact process and extremely increase capacitance of a capacitor in restricted area and improve reliability and yield of a device and realize high integration and miniaturization of a device by alternately disposing capacitors, which are formed around a central word line, in front and backside of a semiconductor substrate.
To achieve the above object, a semiconductor device according to the present invention comprises:
a thin semiconductor substrate;
first and second word lines formed on the thin semiconductor substrate;
a first source, a common drain and a second source formed on the thin semiconductor substrate;
a bit line connected to the common drain;
a first capacitor formed in front of the thin semiconductor substrate, with the first capacitor having a first charge storage electrode connected to the first source, a first dielectric film and a first plate electrode; and
a second capacitor formed in reverse side of the thin semiconductor substrate, with the second capacitor having a second charge storage electrode connected to the second source, a second dielectric film and a second plate electrode.
A method of manufacturing a semiconductor device according to the present invention comprises the steps of:
forming a gate insulation layer, a first word line, a second word line, a first source, a common drain and a second source on a semiconductor substrate;
forming a first inter-insulation layer and forming a bit line electrically connected to the common drain on the first inter-insulation layer;
forming a second inter-insulation layer and forming a first charge storage electrode electrically connected to the first source on said second inter-insulation layer;
sequentially forming a first dielectric film and a first plate electrode on the first charge storage electrode and sequentially forming a third inter-insulation layer and a substrate support layer thereon;
polishing a reverse side of the semiconductor substrate so that the semiconductor substrate is thin;
forming a fourth inter-insulation layer on the reverse side of the thin semiconductor substrate and forming a second charge storage electrode electrically connected to the second source on the fourth inter-insulation layer; and
sequentially forming a second dielectric film, a second plate electrode and a fifth inter-insulation layer on the second charge storage electrode.